This invention relates to MOS transistors and more specifically to methods for manufacturing MOS transistors with a minimum number of masking steps. The invention also relates to double diffused MOS ("DMOS") transistors.
A DMOS transistor is a MOS transistor having a channel length defined by the difference in diffusion of sequentially introduced impurities from a common edge or boundary. One example of a prior art process for manufacturing a DMOS transistor is discussed in U.S. Pat. No. 4,443,931, issued to Baliga, et al., incorporated herein by reference. It is known in the art that it is desirable to manufacture DMOS transistors while minimizing the number of masks used. One reason for this is that by minimizing the numbers of masks, the number of alignment steps is also minimized and therefore the need to accommodate alignment tolerances is minimized. As is known in the art, if the need to accommodate alignment tolerances is minimized, the size and cost of the resulting transistor is minimized.
Another reason for minimizing the number of masking steps it that the complexity of the manufacturing process is correspondingly reduced and thus the cost of producing the transistor is also reduced.